An embodiment of the present invention relates to integrated circuits, and more particularly, to a circuit and method for implementing a standby power-down state in the integrated circuit.
Referring now to FIG. 1, a circuit 10 is shown that can be used to power-gate serially-coupled CMOS inverters U1, U2, U3, U4, and U5 to reduce standby current due to subthreshold leakage. Every other inverter stage U1-U5 uses power-gating devices M5 and M6 to coupled the power terminals of the inverter stages to either VCC or VSS. However, the alternate power-gating method of operating circuit 10 requires that the input and output node voltages for each inverter stage be forced to a specific state for proper functionality. If the wrong data state is used, this technique will not work since the alternate power supply terminals are turned off. In FIG. 1, transistor M3 turns on and forces a low data state at the input node of inverter U1, which results in all subsequent stages U2-U5 going to the necessary standby levels. Transistor M4 is used to avoid contention when transistor M3 is on during standby. Transistor M5 is the positive VCC power supply gating device and transistor M6 is the ground or negative VSS power gating device. The NPG control node is high (goes to VCC or slightly higher than VCC) when circuit 10 is in non-standby mode and goes low when circuit 10 is in standby mode. PPG is low when circuit 10 is in non-standby mode and goes high when circuit 10 is in standby mode.
Asynchronous (ripple-through) logic, as illustrated in circuit 10 of FIG. 1, is relatively easy to use to enable standby states by forcing an early stage node (usually an input stage). However, with synchronous logic, especially where clocked flip-flops or pipelined stages are used, multiple points must be forced when power-gating during low power standby.
Referring now to FIG. 2, circuits 20 and 22 are operated such that nodes within a latch stage are forced to specific logic states during standby mode. The method of operation for circuits 20 and 22 is relatively complicated since it uses a NAND gate U1 in circuit 20 or a NOR gate U4 in circuit 22 as the feedback element and requires an additional transmission gate (M3, M4 is circuit 20 and M7, M8 in circuit 22) in the feedback path.
Circuits 30,40, and 50 is corresponding FIGS. 3, 4, and 5 show an obvious method for setting logic states within latch stages. Each of circuits 30, 40, and 50 addresses how to force the stages based on different conditions of the clock during a low power standby mode. In circuits 30, 40, and 50, one or more xe2x80x9cforcingxe2x80x9d transistors must be added to set node states where the clock blocks signal propagation from a previous stage. In circuit 30 forcing transistors M7 and M11 are shown. In circuit 40 forcing transistors M7 and M12 are shown. In circuit 50 forcing transistors M7, M12, and M11 are shown. Adding two or more forcing transistors as shown in FIGS. 3-5 may not be a problem in some cases. In other cases, however, where latches are placed within a tight physical pitch or when many latches are clocked in parallel, such as for input data latches for embedded memories, it is desirable to minimize unnecessary transistors.
What is desired, therefore, is a circuit and method of operation for implementing a low power supply standby mode in an integrated circuit that uses a single forcing transistor, yet is able to work with synchronous signal paths including latch circuits as well as other logic circuits.
According to the present invention, a signal path in an integrated circuit includes a single forcing transistor coupled to an initial portion of the signal path, at least one transmission gate in the signal path, a clock circuit for forcing the clock inputs of the transmission gate to be conductive during a standby mode, and additional alternate power-gated circuitry in the signal path, wherein a forced data state generated by the single forcing transistor propagates through the entire signal path. The circuit of the present invention works with synchronous circuits including full cycle latches, half cycle latches, as well as combinatorial logic circuits, or combinations thereof.
In a specific embodiment of the invention, a full cycle latch includes a forcing transistor having a gate for receiving a control signal and a drain for receiving an input signal, a first transmission gate having an input for receiving the input signal, a first latch stage having an input coupled to the output of the first transmission gate, a second transmission gate having an input coupled to the output of the first latch stage, a second latch stage having an input coupled to the output of the second transmission gate and an output for providing an output signal, and a clock circuit for forcing the first and second transmission gates to be conductive during a standby mode of operation.
This circuit of the present invention is operated according to a method that reduces the number of nodes that must be forced during a standby mode when using clocked latches. The circuit and method of the present invention can be used with is half-cycle and full cycle latches, even when many stages are cascaded in a pipeline structure.
The circuit of the present invention modifies the clock signals to the transmission gates in a synchronous latch circuit so that a single forcing node data state can be passed through one or more cascaded latch stages.
Other features, objects, and advantages of the present invention are apparent from the accompanying drawings and from the detailed description that follows below.